1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device in which a channel formation region has a smaller thickness than each of a source region and a drain region, and a method for manufacturing the semiconductor device. More specifically, the present invention relates to a semiconductor device in which a channel formation region has a smaller thickness than each of a source region and a drain region and a lightly doped drain (hereinafter referred to as LDD) region is provided between the channel formation region and the drain region, and a method for manufacturing the semiconductor device. The present invention also relates to an electronic appliance using the semiconductor device.
2. Description of the Related Art
It is known that in a thin film transistor (hereinafter referred to as a TFT), a subthreshold swing showing switching characteristics (subthreshold characteristics) of the transistor can be reduced by reducing the thickness of a channel formation region. Here, a subthreshold swing is a gate voltage necessary for increasing a current (subthreshold current) between a source electrode and a drain electrode by one digit, and the smaller a subthreshold swing is, the steeper the slope of the subthreshold current with respect to the gate voltage is and the more excellent the switching characteristics are. By using such a TFT of which a subthreshold swing is small, advantages such as reduction in an off leakage current and suppression of power consumption due to reduction in an operating voltage can be obtained. However, if a whole semiconductor film in which a channel formation region is formed is thinned in order to thin the channel formation region, a source region and a drain region are also thinned; thus, there occur problems such as an increase of sheet resistance in a source region and a drain region and an increase of contact resistance at interfaces between the source region and the source electrode and between the drain region and the drain electrode. Therefore, it is preferable that the thickness of the channel formation region be reduced while the thicknesses of the source region and the drain region are maintained.
Patent Document 1 (Japanese Published Patent Application No. H5-110099) discloses an example of such a technique of thinning only a channel formation region. According to the technique disclosed in Patent Document 1, a channel formation region is thinned as follows. First, a projection is formed at a portion corresponding to a channel formation region over an insulating substrate. A surface of the insulating substrate is partially etched to be removed so that such a projection can be formed. A semiconductor layer formed of silicon or the like is deposited on the insulating substrate including the projection to a given thickness so that a portion corresponding to the projection of the semiconductor layer is raised, and then, an insulating film having a plane surface is formed over the semiconductor layer. Next, a photoresist film is formed over the insulating film in a position corresponding to the projection and ions are injected into the semiconductor layer with the photoresist film used as a mask so that a source region and a drain region are formed in semiconductor layers of both sides of the projection and after that, the photoresist film is removed. Thus, an upper layer portion of the raised portion (that is, the channel formation region) of the semiconductor layer is etched to be removed together with the insulating film to planarize the surface of the semiconductor layer, so that the channel formation region is thinned. The insulating film and the semiconductor layer are etched by plasma etching in a mixed gas atmosphere of SF6 and CHF3. With the technique disclosed in Patent Document 1, when the raised portion of the semiconductor layer, which corresponds to the projection of a surface of an insulator, is thinned, etching is performed until an entire surface of the semiconductor layer is exposed and planarized. Therefore, the source region and the drain region might also be etched together with the raised portion (channel formation region). Further, because plasma etching is used, deterioration of characteristics might occur; for example, an upper portion of the semiconductor layer might be damaged or made to be amorphous and thus, resistance might be increased.
Patent Document 2 (Japanese Published Patent Application No. 2004-281687) discloses another technique of thinning a channel formation region. According to Patent Document 2, a photosensitive resist provided over a semiconductor layer (operation layer) is exposed to light with the use of a halftone mask so that part of the photosensitive resist, which is over the channel formation region in a TFT formation region, is thinner than part of the photosensitive resist, which is over a region other than the channel formation region. Then, the photosensitive resist is further processed so that part of the photosensitive resist, which is over the channel formation region, is removed, and wet etching or dry etching is performed using the remaining part of the photosensitive resist as a mask to thin the channel formation region. However, such selective light exposure of the photosensitive resist with the use of a halftone mask complicates a process and can lead to an increase in manufacturing cost.
On the other hand, a having an LDD structure is known, in which a low concentration impurity region (or an LDD region) is formed between a channel formation region and a drain region and/or between a channel formation region and a source region in order to reduce an off current of the TFT and prevent deterioration of the TFT due to hot carriers. A source region and a drain region are doped with impurities in two steps so that such an LDD region can be formed. More specifically, light doping is performed using a gate electrode as a mask first. Then, a sidewall (for example, silicon oxide) is formed on a side surface of the gate electrode and heavy doping is performed using the gate electrode and the sidewall as masks, so that part of a semiconductor layer, which is located under the sidewall, can be an LDD region. However, in the case where the sidewall is formed in order to the LDD region, steps of manufacturing the TFT are increased. Further, since the sidewall and a gate insulating film are normally formed of the same material as a main component, such a problem might occur that the gate insulating film is also etched at the same time by etching for formation of the sidewall, which undesirably thin the gate insulating film and generate a leakage current. Further, because the LDD region is provided, there occurs a problem that the size (area) of the TFT is increased and thus integration is reduced.
Patent Document 3 (Japanese Published Patent Application No. H5-198594) discloses an example of a technique by which an LDD region can be formed without providing a sidewall and the size of an element can be prevented from being increased. According to Patent Document 3, a light-shielding layer is formed over a quartz substrate with a given space between the light-shielding layer and the quartz substrate and a polycrystalline silicon layer is formed over the quartz substrate and the light-shielding layer, so that a semiconductor layer having an uneven shape is formed. Then, a gate insulating film and a gate electrode are sequentially formed over the semiconductor layer. Then, a resist is applied onto the gate electrode and a rear surface of the quartz substrate is exposed to light by using the light-shielding layer as a mask so that only a region of the resist, in which the light-shielding layer does not exist, remains. Next, the gate electrode and the gate insulating film are etched using the remaining part of the resist as a mask to remove unnecessary parts of the gate electrode and the gate insulating film, and the gate electrode is formed over the semiconductor layer of a depression in an upper portion of the quartz substrate with the gate insulating film interposed therebetween. Then, the gate electrode is used as a mask to introduce impurities into the semiconductor layer by an ion shower method. In that case, two kinds of ion introduction, that is to say, ion introduction at high concentration and a shallow depth and ion introduction at low concentration and a deep depth are performed. Accordingly, impurities are injected at high concentration into the semiconductor layer (the source region and the drain region) of a projected portion over the light-shielding layer. Further, concentration gradient is formed such that the concentration of injected impurities gradually decreases in a depth direction from a surface, in a step portion which connects the semiconductor layer (the channel formation region) of the depressed portion and the semiconductor layer (the source region and the drain region) of the projected portion below the gate electrode; and consequently, the step portion becomes an LDD region.
However, in the case of the semiconductor device and a method for manufacturing the semiconductor device, which are disclosed in Patent Document 3, the channel formation region is formed in the depressed portion of the semiconductor layer, and the source region and the drain region are formed in the projected portions of the semiconductor layer, so that the source region and the drain region are located higher than the channel formation region. Therefore, it is difficult to thin only the channel formation region without adversely affecting the source region and the drain region.
Patent Document 4 (Japanese Published Patent Application No. 2001-230420) discloses that an island-shaped insulating film excellent in thermal conductivity is formed in a predetermined region of a substrate for the purpose of controlling the position and the size of a crystal grain in a semiconductor film by suitably controlling temperature rise in irradiating the semiconductor film with a laser beam for formation of a TFT, so that a step region (projected region) of the semiconductor film, which is located over the island-shaped insulating film, is a channel formation region. Further, Patent Document 5 (Japanese Published Patent Application No. 2002-359376) discloses a dual-gate TFT provided with gate electrodes over and under a channel formation region. Patent Document 6 (Japanese Published Patent Application No. H7-288227) discloses that a number of projections and depressions are formed on a surface of a substrate and a polycrystalline semiconductor film is formed thereover.